Firms or pirates often attempt to analyze the operation and the composition of an integrated circuit chip.
The peeling of the successive interconnection layers of a chip and the analysis thereof is a reverse engineering deprocessing technique enabling to obtain information relative to the chip operation. This technique comprises observing metallizations, for example, made of copper, which form the different connections.
During the analysis of a chip, the elements located on the chip are removed to reach an interconnection layer, which is observed. The metallizations forming that layer, and one or a plurality of insulators surrounding the metallizations, are then removed by etching or polishing, according to the material. The next interconnection layer is thus exposed and can be similarly observed. This layer is then removed in turn, and the process is repeated until observation of all interconnection layers is completed.
Such operations are carried out on a single chip, and not on a full wafer of chips. The key issue of such operations is the ability to accurately remove the layers one by one and to level them properly. Indeed, if certain regions are more (or less) exposed than the neighboring regions, the analysis will be disturbed. For example, such a difference will disturb the rest of the process by causing the etching of materials belonging to an interconnection level different from that considered at a given time, and thus the possible destruction of connections which have not yet been analyzed.
There is a need in the art for a chip structure that makes the implementation of reverse engineering techniques, such as the deprocessing of interconnection layers described here-above, difficult, or even impossible.